In many data processing devices, a store buffer is used to decouple the retirement of store operations to a system bus from a processor or cache of a data processor. The store buffer can contain a number of entries, each of which can store address information, data information, and control information that are to be provided to a bus interface unit during a write operation to memory connected to the system interconnect. In some example embodiments, a cache may be implemented between the store buffer and the processor of the data processing device to facilitate memory accesses by the processor.